主机桥内部交错¶
此 cxl-cli 配置转储显示了以下主机配置
一个具有一个 CXL 根的单插槽系统
CXL 根有四 (4) 个 CXL 主机桥
一 (1) 个 CXL 主机桥连接了两个 CXL 内存扩展器
主机桥解码器被编程为在扩展器之间交错。
此输出由 cxl list -v 生成，并描述了在 /sys/bus/cxl/devices/ 中暴露的对象之间的关系。
[
{
"bus":"root0",
"provider":"ACPI.CXL",
"nr_dports":4,
"dports":[
{
"dport":"pci0000:00",
"alias":"ACPI0016:01",
"id":0
},
{
"dport":"pci0000:a8",
"alias":"ACPI0016:02",
"id":4
},
{
"dport":"pci0000:2a",
"alias":"ACPI0016:03",
"id":1
},
{
"dport":"pci0000:d2",
"alias":"ACPI0016:00",
"id":5
}
],
此段显示 CXL“总线”（root0）有 4 个下游端口连接到 CXL 主机桥。根可以被视为连接到平台内存控制器的单个上游端口，它将内存请求路由到该控制器。
ports:root0 部分说明了每个下游端口的配置方式。如果端口未配置（ID 为 0 和 1），则会省略它们。
"ports:root0":[
{
"port":"port1",
"host":"pci0000:d2",
"depth":1,
"nr_dports":3,
"dports":[
{
"dport":"0000:d2:01.1",
"alias":"device:02",
"id":0
},
{
"dport":"0000:d2:01.3",
"alias":"device:05",
"id":2
},
{
"dport":"0000:d2:07.1",
"alias":"device:0d",
"id":113
}
],
此段显示了与 CXL 主机桥 port1 相关联的可用下游端口。在此示例中，port1 有 3 个可用下游端口：dport1、dport2 和 dport113。
"endpoints:port1":[
{
"endpoint":"endpoint5",
"host":"mem0",
"parent_dport":"0000:d2:01.1",
"depth":2,
"memdev":{
"memdev":"mem0",
"ram_size":137438953472,
"serial":0,
"numa_node":0,
"host":"0000:d3:00.0"
},
"decoders:endpoint5":[
{
"decoder":"decoder5.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"dpa_resource":0,
"dpa_size":137438953472,
"mode":"ram"
}
]
},
{
"endpoint":"endpoint6",
"host":"mem1",
"parent_dport":"0000:d2:01.3,
"depth":2,
"memdev":{
"memdev":"mem1",
"ram_size":137438953472,
"serial":0,
"numa_node":0,
"host":"0000:a9:00.0"
},
"decoders:endpoint6":[
{
"decoder":"decoder6.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"dpa_resource":0,
"dpa_size":137438953472,
"mode":"ram"
}
]
}
],
此段显示了连接到主机桥 port1 的端点。
endpoint5 包含一个已配置的解码器 decoder5.0，它属于相同的交错配置内存区域（稍后显示）。
接下来是属于主机桥的解码器
"decoders:port1":[
{
"decoder":"decoder1.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"nr_targets":2,
"targets":[
{
"target":"0000:d2:01.1",
"alias":"device:02",
"position":0,
"id":0
},
{
"target":"0000:d2:01.3",
"alias":"device:05",
"position":1,
"id":0
}
]
}
]
},
主机桥 port1 有一个单独的解码器 (decoder1.0)，具有两个目标：dport1 和 dport3 — 它们分别连接到 endpoint5 和 endpoint6。
主机桥解码器以 256 字节的粒度交错这些设备。
下一段显示了三个未连接端点的 CXL 主机桥。
{
"port":"port2",
"host":"pci0000:00",
"depth":1,
"nr_dports":2,
"dports":[
{
"dport":"0000:00:01.3",
"alias":"device:55",
"id":2
},
{
"dport":"0000:00:07.1",
"alias":"device:5d",
"id":113
}
]
},
{
"port":"port3",
"host":"pci0000:a8",
"depth":1,
"nr_dports":1,
"dports":[
{
"dport":"0000:a8:01.1",
"alias":"device:c3",
"id":0
}
],
},
{
"port":"port4",
"host":"pci0000:2a",
"depth":1,
"nr_dports":1,
"dports":[
{
"dport":"0000:2a:01.1",
"alias":"device:d0",
"id":0
}
]
}
],
接下来是属于 root0 的 根解码器。此根解码器以 256 字节的粒度在下游端口 port1 和 port3 之间应用交错。
此信息由 CXL 驱动程序读取 ACPI CEDT CMFWS 生成。
"decoders:root0":[
{
"decoder":"decoder0.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":1,
"max_available_extent":0,
"volatile_capable":true,
"nr_targets":2,
"targets":[
{
"target":"pci0000:a8",
"alias":"ACPI0016:02",
"position":1,
"id":4
},
],
最后，我们有与 根解码器 decoder0.0 相关联的 内存区域。此区域描述了交错集的整体交错配置。
"regions:decoder0.0":[
{
"region":"region0",
"resource":825975898112,
"size":274877906944,
"type":"ram",
"interleave_ways":2,
"interleave_granularity":256,
"decode_state":"commit",
"mappings":[
{
"position":1,
"memdev":"mem1",
"decoder":"decoder6.0"
},
{
"position":0,
"memdev":"mem0",
"decoder":"decoder5.0"
}
]
}
]
}
]
}
]